Floating gate cells are known in the art. FIGS. 1A and 1B, to which reference is now made, illustrate the standard circuit indication and the physical shape of an exemplary floating gate cell. FIG. 1C, to which reference is also made, illustrates the floating gate cell in an active state.
Each floating gate cell is built on a substrate 8 (FIG. 1B) in which are created a source 10 and a drain 12. A channel 13 exists between the source 10 and drain 12. On top of the substrate 8 are a control gate 14 and a floating gate 16, the latter of which can programmably store charge therein. If the floating gate stores charge, the cell is said to be programmed to a "0" state. Otherwise, if no charge is stored in the floating gate 16, the cell is in a "1" state. Each floating gate cell stores a single bit of data, which is either in the "0" or "1" state.
Extensive efforts have been made to shrink the cell size in floating gate cell memory arrays where the smaller the cell size, the smaller the integrated circuit die or chip containing a given number of floating gate cells and, therefore, the higher the yield of useful semiconductor dice in the manufacturing process. Moreover, because a smaller cell size results in a smaller integrated circuit die for a given size array, more semiconductor die can be obtained from a given sized wafer and thus, the manufacturing cost per die is lower. Accordingly, efforts have been made to reduce the size of the floating gate cell and/or to apply a more dense array architecture, such as with a virtual ground architecture. An example of a reduced size array architecture is the alternate metal, virtual ground (AMG) architecture, described in U.S. Pat. No. 5,151,375, assigned to the common assignees of the present invention.
The floating gate cell size is reduced by reducing the minimum "design rule" defining the minimum size (length and/or width) of certain elements, such as the control gate 14, the floating gate 16 and sometimes, of the drain 12 and source 10, of the floating gate cell. Design rules of 0.8 .mu.m and smaller are known in the art. However, it is noted that the design rules cannot get infinitely smaller without affecting the functionality of the floating gate cell.
To read the information stored in the floating gate 16, a drain voltage is placed on the drain 12 and the source 10 is connected to ground. The gate is connected to a gate voltage V.sub.g and the cell is monitored for any current in the channel 13.
If the floating gate 16 is not charged (e.g. the "1" state), the threshold level V.sub.t of the cell is quite low. For example, it might be less than 2V. The effective gate voltage available to turn on the channel, which is the gate voltage V.sub.g less the threshold voltage V.sub.t, effectively is, accordingly, sufficiently large and thus, induces depletion and inversion layers 20 and 22, respectively, (FIG. 1C) in the channel 13. The depletion layer 20 has positive ions in it and the inversion layer 22, which is at the surface of substrate 8 within the channel 13, has free electrons in it. Under the influence of the electric field generated by the voltage on the control gate 14, the free electrons move within the inversion layer 22 from the source 12 to the drain 10, thereby creating a measurable current within the channel 13.
If the floating gate 16 is charged, the threshold level V.sub.t of the cell is close to the gate voltage V.sub.g. For example, it might be greater than 4.5V. Accordingly, the effective gate voltage (V.sub.g -V.sub.t) is relatively small and, therefore, no significant channel current is flowing. Accordingly, the cell is turned off.
In order to increase the data density of a memory array, without significantly increasing its size, integrated circuit designers have designed multi-bit floating gate cells. These cells are similar to the one shown in FIG. 1B but have a multiplicity of threshold voltages defined therefor. Each threshold voltage defines a different bit state. For example, a cell might have four threshold voltages defined where the lowest voltage might indicate a "00" state, the second lowest voltage might indicate a "01" state, the third lowest might indicate a "10" state and the fourth voltage might indicate a "11" state.
These multi-threshold floating gate cells utilize the same real estate in the memory portion of the memory array; however, they require more complicated sensing apparatus (to differentiate among the four voltage states) which occupies a larger portion of the array.
The following prior art references are related to multibit semiconductor memory cells: U.S. Pat. No. 5,021,999 to Kohda et al., U.S. Pat. No. 5,214,303 to Aoki, U.S. Pat. No. 5,394,355 to Uramoto et al., U.S. Pat. No. 5,414,693 to Ma et al. and U.S. Pat. No. 5,434,825 to Harari.